Chipmakers now run silicon tests over PCIe, slashing test time and cost

Siemens and Teradyne have teamed up to let engineers test advanced AI and data center chips using the same PCIe or USB ports the chips already have, instead of dedicated test ports. Their solution, Tessent Streaming Scan Network, packages scan test data into efficient packets that flow through standard high-speed interfaces.

For chip design and test teams, this means one consistent programming model from initial engineering all the way to mass production. Test patterns created during the design phase work directly on the factory floor, eliminating months of rework and separate team handoffs. The result is significantly faster testing and lower costs for complex chiplets and multi-core processors.